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ML1001
ML1001 Series Static LCD COG Driver
v Application
u u u u Instrument LCD Module Telephone LCD Module Automotive LCD Module Handheld Device LCD Module
v Features
l l l l l l l l l A Gold Bump Chip without external component. Logic & LCD power supply: 2.0V to 6.0V Typical Current consumption: 25uA at VIN = 3V & no load condition. Number of segments: 40 Cascade the ML1001 to form a single piece of 80 or 120 segments LCD driver. Simple 3 pin microcontroller interface through DIN, DCLK & LOAD. Blink of the display data. Offer best contrast and widest viewing angle of TN LCD technology. No temperature compensation needed for Topr = -40oC to 80oC.
v General Description
ML1001 static LCD COG (chip on glass) driver is 40 segments LCD driver with gold bump. It can be cascaded to form a single piece of 80 or 120 segments LCD drivers. It targets at custom TN LCD COG Module product which requires the best quality of TN LCD technology. With the use of ML1001 series driver, it offers the best contrast, the widest viewing angle, the widest range of operating voltage and the widest range of operating temperature when compared to the multiplex method. Our ML1001 includes an internal 32kHz oscillator, a 40-bit shift register, a 40-bit data register, a 16-bit segment driver, a 24-bit segment driver, two common drivers, a blink control circuit, a power-up reset circuit and a frequency divider which offer the necessary clock signals for Blink control, segment & common driver circuit. Through the DIN pin, the display data is serially shifted into the 40-bit shift register at the rising edge of DCLK signal. The display data, which is going to be displayed on the attached LCD, is then stored in the 40-bit data register at the rising edge of the LOAD signal. Other features like blinking of the display data by the BEN and BCLK, disable the internal oscillator by the OEN, input an external clock signal to the FIN, and enable or disable the segment and common driver by the SEN1, SEN2, CEN1A and CEN1B, are included.
v Ordering Information
Part Number ML1001-1U ML1001-2U ML1001-3U Description a 40 segment static LCD driver a 80 segment static LCD driver a 120 segment static LCD driver Package Form Gold Bump Die Gold Bump Die Gold Bump Die
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ML1001
v Block Diagram
CEN1A COM1A SEN1 S1 S16 SEN2 S17 S40 CEN1B COM1B
LCLK Common Driver 16-bit Segment Driver 24-bit Segment Driver Common Driver
LOAD 40-bit Data Register Blink Control
BEN BCLK
DIN DCLK 40-bit Shift Register Power-Up Reset OEN Oscillator Frequency Divider
DOUT
OOUT
FIN 2KHz 1KHz 500Hz 250Hz 125Hz 4Hz
2Hz
1Hz
v Absolute Maximum Ratings
Parameter Supply voltage Supply Current Input Voltage Output Voltage DC input Current DC output Current Storage temperature Total power dissipation Symbol Condition VDD IDD VDD = 3V, no Load VIN VOUT IIN IOUT Tstg Ptot MIN -0.5 -50 GND-0.3 GND-0.3 -10 -10 -65 MAX +7.0 +50 VDD +0.3 VDD +0.3 +10 +10 +150 400 Unit V mA V V mA mA o C mW
2/13
ML1001
v DC Characteristic
VDD = 3.0V; Tamb = 25oC ; unless otherwise specified Parameter Symbol Condition Supplies Supply voltage VDD Supply Current IDD Disable Oscillator Supply Current IDD Enable Oscillator Logic LOW-level input voltage VIL HIGH-level input voltage VIH LOW-level output IOL VOL = 1.0V current HIGH-level output IOH VOH = 2.0V current LCD outputs Output resistance at pads RSEG S1 to S40 Output resistance at pads RCOM COM1A and COM1B MIN 2.0 GND 0.7*VDD 1 -1 TYP 0.1 25 MAX 6.0 0.5 60 0.3*VDD VDD Unit V uA uA V V mA mA
-
85 45
150 100
ohm ohm
v AC Characteristic
VDD =3.0V; Tamb = 25oC; unless otherwise specified Parameter Symbol Conditions Oscillator frequency at foout pad OOUT FIN, LOAD, DIN, DCLK tH High time FIN, LOAD, DIN, DCLK tL Low time FIN, LOAD, DIN, DCLK tr Rise time FIN, LOAD, DIN, DCLK tf Fall time DCLK Frequency FDCLK MIN 21 0.4 0.4 1 TYP 32 MAX 48 10 10 1,000 Unit kHz us us us us kHz
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ML1001
v Timing Diagram
1/FDCLK tr
FIN, DIN, DCLK, LOAD VIH VIL
tH
tf
VIH VIL
tL
VIH VIL
DIN
DCLK
40, 80 or 120 DCLKS
LOAD
v Functional Description
The ML1001 is a static LCD COG (chip on glass) driver which can drive upto 40 segments or cascaded with two or three ML1001s to drive 80 & 120 segments. There is a shift register for serially shifting in the data and a data register to store the data that is going to be displayed. The display data is read into the shift register serially through the DIN pin at the rising edge of the DCLK signal. The display data will then be displayed at the rising edge of the LOAD signal. The display data in the shift register is output by the DOUT pin after 40 rising edges of the DCLK signal. The display data should be input in the sequence of SEG40, SEG39... SEG2, SEG1 for proper display of data. i) Power on reset At Power on the ML1001 resets to a starting condition as follows: 1. The shift register outputs are set to GND. 2. The data register outputs are set to GND, hence all LCD segments off.
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ML1001 ii) Oscillator a) Internal clock The internal logic and the LCD driving signal of ML1001 are clocked either by the built-in oscillator or from an external clock. When the internal oscillator is used, OEN should be connected to GND and the OOUT should be connected to FIN. The oscillator will oscillate at 32 kHz and the frequency is independent in the range of 2.0V < VDD < 6.0V . b) External clock When using an external clock, the OEN is connected to VDD then connects the external clock to FIN. iii) Timing ML1001 have several frequencies of clock signal for the users to choose for the LCD display clock (ie. LCLK) and the blink clock (ie. BCLK). They include the following clock signals : Frequency of Clock Signal at FIN = 32 kHz 2 KHz 1 KHz 500 Hz 256 Hz 128 Hz 4 Hz 2 Hz 1 Hz iv) Segment outputs ML1001 has 40 segment outputs which should be connected directly to the LCD. If less than 40 segments are required, the unused segments should be left open circuit. Users can disable the first 1 to 16 segments and the last 17 to 40 segments by connecting the SEN1 and SEN2 to VDD, respectively. The segment outputs shall output GND level after disabling it. v) Common outputs ML1001 consists of 2 common signals (ie. COM1A & COM1B). These two common signals are the inversion of the LCLK. The common outputs should be left open-circuit if the outputs are unused. Users can disable the COM1A and COM1B by connecting the CEN1A and CEN1B to VDD, respectively. The common outputs will change to GND after disabling it. vi) Blink ML1001 has a blink function that users shall connect the BEN to GND and input the blink clock (ie. BCLK) either by connecting ML1001 output clock signal from Frequency Divider or an external clock signal. Users shall disable blink function by connecting BEN to VDD. Actual Divider of FIN 1/16 1/32 1/64 1/128 1/256 1/8192 1/16384 1/32768 Target Input Pin
LCLK
BCLK
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ML1001
v Pad Configuration
71 70 69 68 67 66 65 64 63 62 60 61 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
72 73 74 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
31 30 29
ML1001
Chip Size : Part Number ML1001-1U ML1001-2U ML1001-3U
Description a 40 segment static LCD driver a 80 segment static LCD driver a 120 segment static LCD driver
Chip Size 3,440 um x 600 um 6,880 um x 600 um 10,320 um x 600 um
Chip Thickness : 400 um + 25 um Gold Bump Pad Size : 32 um x 72 um Gold Bump Height : 18 um + 2 um Note : 1. The die faces up in the diagram.
6/13
ML1001
v Pad Location
All x and y coordinates are references to the left lower corner of the chip.
PAD Num. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PAD Name LOAD DIN DCLK BEN OEN VDD SEN1 CEN1A SEN2 CEN1B GND OOUT FIN LCLK 2 KHz 1 KHz 500 Hz 250 Hz 125 Hz 4 Hz 2 Hz 1 Hz BCLK LCLK BEN Coordinate X 20 120 220 320 420 520 600 700 800 900 1000 1080 1180 1280 1360 1440 1520 1600 1680 1760 1840 1920 2020 2120 2220 Y 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 PAD Num. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PAD Name DCLK DOUT LOAD GND VDD COM1B S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 Coordinate X 2320 2400 2500 2826 2826 2826 2806 2726 2646 2566 2486 2406 2326 2246 2166 2086 2006 1926 1846 1766 1686 1606 1526 1446 1366 Y 40 40 40 60 140 220 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 PAD Num. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 PAD Name S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 COM1A VDD GND Coordinate X 1286 1206 1126 1046 966 886 806 726 646 566 486 406 326 246 166 86 6 -74 -154 -234 -314 -294 -294 -294 Y 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 220 140 60
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ML1001
v Pin Description
Symbol LOAD DIN DCLK BEN OEN VDD SEN1 CEN1A SEN2 CEN1B GND OOUT FIN LCLK 2 kHz 1 kHz 512 Hz 256 Hz 128 Hz 4 Hz 2 Hz 1 Hz BCLK DOUT GND VDD COM1B S40 to S1 COM1A VDD GND Pad 1,28 2 3,26 4,25 5 6 7 8 9 10 11 12 13 14,24 15 16 17 18 19 20 21 22 23 27 29 30 31 32 to 71 72 73 74 Description Load data from the shift register to data register; note 1 Display data input pin Input pin for the clock of the display data; note 1 Enable pin of the blink function; note 1, note 2 Enable pin of the internal oscillator; note 2 Supply voltage Enable pin of the segment from S1 to S16; note 1 Enable pin of the COM1A; note 2 Enable pin of the segment from S17 to S40; note 1 Enable pin of the COM1B; note 2 Logic ground Output pin of the internal oscillator Input pin of the external/internal clock Input pin to the LCD display clock; note 1 Output 1/16 frequency of the input to the FIN; note 3 Output 1/32 frequency of the input to the FIN; note 3 Output 1/64 frequency of the input to the FIN; note 3 Output 1/128 frequency of the input to the FIN; note 3 Output 1/256 frequency of the input to the FIN; note 3 Output 1/8192 frequency of the input to the FIN; note 3 Output 1/16384 frequency of the input to the FIN; note 3 Output 1/32768 frequency of the input to the FIN; note 3 Input pin for the blink clock Output pin for 40-bit Shift register, it shall connect to DIN of next ML1001 Logic ground Supply voltage Common driving signal to LCD panel LCD segment outputs Common driving signal to LCD panel Supply voltage Logic ground
Note : 1. In cascade format of ML1001(ie. ML1001-2U and -3U), one pin is the input of current ML1001 and the other is for the connection with the corresponding input pin of next ML1001. 2. All Enable pins are active low. 3. Condition : FIN = 32 KHz Clock.
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ML1001
v Application Examples
ML1001-1U Standard Application Pin Number 1 2 3 4 5 6 Pin Name VDD GND LOAD DIN DCLK CHECK
ML1001-1U Application Circuit with 1 Hz Blink Feature Pin Number 1 2 3 4 5 6 7 Pin Name VDD GND LOAD DIN DCLK BEN CHECK
Note : Blink at 1 Hz if BEN = 0V, Normal Display if BEN = VDD. ML1001-1U Application Circuit with External 32 KHz Clock Pin Number 1 2 3 4 5 6 7 Pin Name VDD GND LOAD DIN DCLK FIN CHECK
Note : If External 32 KHz Clock Signal is available, designer can turn off Internal Oscillator to save power.
Note : Pin LOAD and Pin CHECK shall be connected together if the flip-chip assembly is in good condition. Hence, Pin CHECK can be served for qualifying the flip-chip assembly quality.
9/13
ML1001
ML1001-2U Standard Application Pin Number 1 2 3 4 5 6 Pin Name VDD GND LOAD DIN DCLK CHECK
Note :
Chip 1 Pad Coordinate shall follow "Table of Pad Location". Chip 2 Pad Coordinate shall be calculated as follow : Chip 2 X-Coordinate = Chip 1 X-Coordinate + 3,440um Chip 2 Y-Coordinate = Chip 1 Y-Coordinate
10/13
ML1001
ML1001-3U Standard Application Pin Number 1 2 3 4 5 6 Pin Name VDD GND LOAD DIN DCLK CHECK
Note :
Chip 1 Pad Coordinate shall follow "Table of Pad Location". Chip 2 Pad Coordinate shall be calculated as follow : Chip 2 X-Coordinate = Chip 1 X-Coordinate + 3,440um Chip 2 Y-Coordinate = Chip 1 Y-Coordinate Chip 3 Pad Coordinate shall be calculated as follow : Chip 3 X-Coordinate = Chip 1 X-Coordinate + 6,880um Chip 3 Y-Coordinate = Chip 1 Y-Coordinate
11/13
ML1001
v Typical Characteristics
1) Supply Current vs. Frequency of LCLK
Load = 25nF 1600 VDD = 6V 1400 1200 Supply Current ISS(uA) 1000 VDD = 4V 800 VDD = 3V 600 400 VDD = 2V 200 0 0 500 1000 1500 2000 2500 LCD Frequency LCLK(Hz) 100 No Load 0 0 1 2 3 4 5 6 7 Input Voltage VIN(V) 700 With Load Supply Current ISS(uA) VDD = 5V 600 500 400 300 200 800
2) Supply Current vs. Input Voltage
Load = 25nF
3) Example of Contrast Ratio vs. Input Voltage
12 10 Contrast Ratio 8
4) Example of Contrast Ratio vs. Viewing Angle
VIN = 3V 12 10 Contrast Ratio 8 ML1001 Static TN COG Module 6 4 1/3 Duty LCD 2
6 4 2 0 0.0 V 1.0 V 2.0 V 3.0 V 4.0 V 5.0 V 6.0 V Input Voltage VIN(V)
0 0 10 20 30 40 50 60 70 80 Viewing Angle (degree)
Note: 1. Contrast ratio of LCD shall vary from the Liquid Crystal used. 2. Contrast ratio of 1/3 Duty LCD is shown on graph 4 for comparison only. 3. The viewing angle is measured from the normal of LCD as shown below.
0 degree
Observer Viewing Angle
LCD
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ML1001
v History of Revision
REV
DESCRIPTION First Official Specification
DATE 8/11/02
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. 13/13

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